74104

SKU: 74104

BRAND: Communica


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Delivery time: 2-5 working days for South Africa
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Gated J-K Master –Slave Flip Flop 14PIN DIP

Specifications

  • Logic Family:TTL (74xx series)
  • Package:14-pin DIP (through-hole)
  • Number of Flip-Flops:2 (dual)
  • Type:Gated J-K master–slave flip-flop
  • Triggering:Clocked, master–slave configuration
  • Outputs:Q and Q̅ (complementary)
  • Asynchronous Inputs:Preset and Clear (active LOW, typical)
  • Supply Voltage (Vcc):75 V – 5.25 V (nominal 5 V)
  • Absolute Max Vcc:~7 V
  • Input Voltage Range:–0.5 V to Vcc
  • Logic HIGH (VIH):≥ 2.0 V
  • Logic LOW (VIL):≤ 0.8 V
  • Output HIGH (VOH):≥ 2.4 V
  • Output LOW (VOL):≤ 0.4 V
  • Propagation Delay:~20–35 ns (typical, depends on load)
  • Power Dissipation:~10–25 mW per flip-flop (typical TTL)
  • Operating Temperature:0 °C to 70 °C (commercial range)

Typical Applications

  • Counters and registers
  • Frequency division
  • State machines
  • Control logic
  • Toggle and memory elements

Additional Information

Device Gated J-K Master
Enhance your digital circuits with the 74104 Gated J-K Master-Slave Flip Flop. This dual flip-flop offers precise clocked operation and versatile asynchronous inputs, making it ideal for counters, state machines, and control logic. With a reliable TTL design and a wide supply voltage range, it's perfect for any project requiring efficient data storage and processing.

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