Gated J-K Master –Slave Flip Flop 14PIN DIP
Specifications
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Logic Family:TTL (74xx series)
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Package:14-pin DIP (through-hole)
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Number of Flip-Flops:2 (dual)
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Type:Gated J-K master–slave flip-flop
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Triggering:Clocked, master–slave configuration
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Outputs:Q and Q̅ (complementary)
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Asynchronous Inputs:Preset and Clear (active LOW, typical)
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Supply Voltage (Vcc):75 V – 5.25 V (nominal 5 V)
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Absolute Max Vcc:~7 V
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Input Voltage Range:–0.5 V to Vcc
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Logic HIGH (VIH):≥ 2.0 V
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Logic LOW (VIL):≤ 0.8 V
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Output HIGH (VOH):≥ 2.4 V
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Output LOW (VOL):≤ 0.4 V
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Propagation Delay:~20–35 ns (typical, depends on load)
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Power Dissipation:~10–25 mW per flip-flop (typical TTL)
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Operating Temperature:0 °C to 70 °C (commercial range)
Typical Applications
- Counters and registers
- Frequency division
- State machines
- Control logic
- Toggle and memory elements
Additional Information
Enhance your digital circuits with the 74104 Gated J-K Master-Slave Flip Flop. This dual flip-flop offers precise clocked operation and versatile asynchronous inputs, making it ideal for counters, state machines, and control logic. With a reliable TTL design and a wide supply voltage range, it's perfect for any project requiring efficient data storage and processing.