Dual Negative-Edge-Triggered J-K flip-flops
Specifications
Electrical Characteristics
- Supply Voltage (Vcc): 4.75V – 5.25V
- Input Voltage High (VIH): Min 2V
- Input Voltage Low (VIL): Max 0.8V
- Output Voltage High (VOH): Min 2.7V at IOH = –0.4 mA
- Output Voltage Low (VOL): Max 0.5V at IOL = 8 mA
- Propagation Delay (Clock to Q): Typical 15 ns
- Power Dissipation: Approx. 20 mW per device
Absolute Maximum Ratings
- Supply Voltage (Vcc): 7V
- Input Voltage: –0.5V to 7V
- Operating Temperature: 0°C to +70°C (Commercial)
- Storage Temperature: –65°C to +150°C
Additional Information
Unlock precision in your digital circuits with the 74LS113 Dual Negative-Edge-Triggered J-K flip-flop. With a fast propagation delay of 15 ns and low power dissipation, this reliable IC ensures efficient performance for your electronic projects. Ideal for enhancing logic designs, it operates smoothly within a supply voltage range of 4.75V to 5.25V, making it a perfect choice for both hobbyists and professionals. Elevate your designs today!